3 PCB Layout Principles for ESD Protection

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Electrostatic discharge, or ESD, can be defined as a momentary electric current flow between two electrically charged objects or materials. For sensitive electronic equipment, an ESD event can be destructive, as the voltage here can reach thousands of volts.

There are different ways to provide integrated circuits with ESD protection. One of them is to use overvoltage protection devices. Electronics engineers usually use transient voltage suppressor (TVS) diodes. This protection can be further enhanced with proper printed circuit board design.

Here are three PCB layout rules that will help you protect circuits from ESD events. 

1. Optimize impedances around the TVS diode

A TVS diode is placed in parallel with the circuit you want to protect. However, any PCB component and traces have parasitic inductances (more details). In a typical ESD protection scheme, there are four inductances:

  • L1 and L2 between the ESD Source and the TVS;
  • L3 between the TVS and ground;
  • L4 between the TVS and the Protected IC.

L4 must be larger than other inductances so that an electrostatic discharge is forced to ground. One can do it by placing the TVS as close to the ESD Source (usually a connector) as possible, while moving the Protected IC further from the TVS. The distance between the ESD Source and the TVS must be shorter than the distance between the TVS and the Protected IC. Additionally, the TVS must be placed directly on the Protected Line to minimize L2. 

2. Limit electromagnetic interference

ESD events cause electromagnetic interference. The rapidly changing electric field created by ESD can couple onto nearby circuits. This, in turn, can cause undesired voltages on unintended circuits. The main sources of EMI are the traces between the ESD Source and the TVS. Therefore, one must not route unprotected circuits in this area. Also, the TVS must be mounted as close to the ESD Source as rules allow.

Another way to limit electromagnetic interference is to use short and straight traces between the ESD Source and the TVS. If it is not possible, one can use curves with angles not exceeding 45°. 

3. Use VIAs properly

If one uses a multilayer PCB, VIAs serve as traces that also have parasitic inductances, says Analog. Thus, if the ESD Source and the Protected IC are located on the same layer, while the TVS is located on another layer, the electrostatic discharge will branch between the IC and the TVS. As a result, the circuit can still be damaged.

ESD protection can be enhanced with the proper use of VIAs. It is not recommended to place the Protected IC and the ESD Source on the same layer. So, the best solution is to place the ESD Source and the TVS on the same layer, and the Protected IC on another layer. This way, the ESD current will first flow through the TVS before reaching the IC.

If this layout is impossible, one should use two VIAs: one connecting the ESD Source to the TVS protection pin (on another layer) and another one connecting the TVS to the Protected IC (one the same layer as the ESD Source). This way, the ESD current is forced to the pin before it can reach the circuit.

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